In recent years, ReRAM (Resistive Random Access Memory) that stores, in a non-volatile manner, resistance value information, for example, a high resistance state and a low resistance state, of an electrically rewritable variable resistive element is given attention for the non-volatile memory device. With respect to such ReRAM, a structure where a memory cell array, in which a variable resistance memory cell having a variable resistive element serving as a memory element and a rectifier element such as a diode connected in series is arrayed to an array shape at an intersection of a plurality of word lines extending parallel to a first direction and a plurality of bit lines extending parallel to a second direction perpendicular to the first direction, is stacked in plurals, and the word line or the bit line is shared between the memory cell arrays adjacent in a stacking direction is known.
Such non-volatile memory device may be manufactured in the following manner. A first wiring material layer, which becomes the word line, and a first memory layer including a variable resistive layer, which becomes the variable resistive element, and a diode layer, which becomes a rectifier element, are stacked on an inter-layer insulating film. The first wiring material layer and the first memory layer are then etched to a line-and-space pattern extending in the first direction through a lithography technique and a reactive ion etching technique (hereinafter referred to as RIE method), and the inter-layer insulating film is filled between the patterns. The first wiring material layer thus becomes the word line. Thereafter, a second wiring material layer, which becomes the bit line, and a second memory layer including the variable resistive layer and the diode layer are stacked on the inter-layer insulating film, and the second memory layer, the second wiring material layer, the first memory layer, and the inter-layer insulating film are etched to a line-and-space pattern extending in the second direction by the lithography technique and the RIE method, and the inter-layer insulating film is filled between the patterns. The second wiring material layer thus becomes the bit line, and a first layer of memory cell array in which a memory cell having a column structure is arranged in a matrix shape at a cross-point of the word line and the bit line is formed. Thereafter, similar processes are repeated to form plural layers of memory cell arrays.
In a memory cell section in which the word line and the bit line intersect, a memory cell configuring member that configures the memory cell exists in a lower layer portion of the wiring material layer to become the word line or the bit line, but the memory cell configuring member does not exist and an inter-layer insulating film made of SiO2 normally exists at the lower layer portion of the wiring material layer in a drawing section of only the word line or only the bit line connecting between the memory cell section and a contact section.
In the conventional art, the inter-layer insulating film is sufficiently etched to suppress the short-circuit between the adjacent memory cells in the memory cell section when collectively processing the memory cell configuring members for two layers. As a result, the aspect ratio becomes large since the inter-layer insulating film at the lower layer becomes too etched in the drawing section, the stress difference between the memory cell configuring member such as the wiring material layer and the inter-layer insulating film becomes emphasized, and the pattern may become twisted.